Altera DK-START-5AGXB3N-产品快照
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- Altera
- 型号:
- DK-START-5AGXB3N
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产品介绍
Altera DK-START-5AGXB3N
Arria V GX FPGA Starter Development Kit
Altera
Arria V GX FPGA Starter Kit, Altera The Altera Arria® V GX FPGA Starter Kit includes all the hardware and software you need to develop cost-sensitive FPGA applications immediately. It features a High-Definition multimedia interface (HDMI) and Serial Digital Interface (SDI) connectors. FPGAArria V GX 5AGXFB3H4F35C5NSystem controller: MAX V 5M2210ZF256C4N devicePower monitor GUIAnalogue-to-digital converter (ADC) with eight channelsNon-isolated power railFast passive parallel (FPP) x16 mode through parallel Flash loader (PFL)Control and status registersEmbedded USB-Blaster II: MAX II EPM570GM100C4N deviceHDMI 1.3 TX4 x XCVR, 2.7Gbps (max by level shifter) and 270MHz Tx clock HDMI Tx connectorSTMicroelectronics HDMI level shifter STHDLS101TLevel shift XCVR PCML 1.5V TMDS levelDDC and HPD HDMI compliant levelData channel up to 2.7Gbps; HDMI 1.3 compliantClock channel up to 270MHz; enough to support 2.7Gbps data rateHDMI specification: clock period = 10x of UISDI 3G XCVR Tx/Rx loopback2 x SMB connectors (cable not included in kit)Up to 2.97GbpsUses National Semiconductor driver/receiver LMH0384SQ/LMH0303SQxRequires 148.5MHz and 148.35MHz at XCVR refclk to support US and EU standard respectivelyUse VCXO to fine tune and lock to the recovered CDR frequencyHSMC 8 x XCVR up to 6.375GbpsNot compliant to PCI Express (PCIe) HIP pin assignment4 x CMOS8 x Tx and 9 x Rx differential interface using dedicated Tx/Rx channels2 x low-voltage differential signalling (LVDS) clock in2 x differential clock outI2C busJTAGMinimum current support: 2A @ 3.3V, 1A @ 12VDedicated clock domain from Si 5338 clock generator for xcvr refclkHSMC loopback with BTS GUISMA XCVR Tx/Rx channelLVPECL clock inputLVPECL clock outputDedicated clock domain from Si 5338 clock generator for xcvr refclkDDR3 SDRAMMicron MT41J64M16LA-15E DDR3 SDRAM 8M x 16 x 8Two devices: 2 x 16 width = x32BTS DDR3 SDRAM GUI using Uniphy and high performance (HP) controller IISSRAM 512K x 36, 18Mb ISSI IS61VPS51236AShared address or data with FlashUser IO LCD character display4 x DIP switch3 x pushbuttons4 x LEDsConfiguration FPP x16 modeDual Flash 512Mbit Numonyx PC28F512P30BF (52MHz fMAX)JTAG headerEmbedded USB Blaster II Cypress Microcontroller CY7C68013A as USB PHY 2.0MAX II deviceEthernet 10/100/1000 Base-TRJ-45 connector, on-board LED for link statusMarvell Ethernet PHY 88E1111Requires 50MHz clock from CLKIN Supplied with Loopback and debug header daughter cards, USB cable, 75Ω SMB video cable, Ethernet cable, license for the Development Kit Edition (DKE) of the Quartus II software (Windows platform only). Field Programmable Gate Arrays (FPGA) An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB. ; Classification Development Kit; Technology FPGA, PCI;
Semiconductors>Semiconductor Development Kits>Programmable Logic Development Kits
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